Interface level-shifter dual-rail memory architecture
US12340864B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 8, 2023 |
| Grant date | Jun 24, 2025 |
| Priority date | — |
| Expiry date | Jul 2, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/12005
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes clock signal generation circuitry, and first integrated level shifter and latch circuitry. The clock signal generation circuitry receives a first clock signal and an isolation signal, and generates a second clock signal based on the first clock signal and the isolation signal. The isolation signal corresponds to a power state of a power supply associated with the first clock signal. The first integrated level shifter and latch circuitry receives an input signal in a first power supply domain, and latches a value the input signal based on the second clock signal. Further, the first integrated level shifter and latch circuitry outputs, based on the latched value, an output signal in a second power supply domain different than the first power supply domain.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.