Reduced circuit area memory device with a half-word memory architecture
US12340865B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | May 4, 2023 |
| Grant date | Jun 24, 2025 |
| Priority date | — |
| Expiry date | Jan 3, 2044 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/848
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes a memory device and control circuitry. The memory array includes bitcells and bitlines connected to the bitcells. The bitcells are grouped into bitcell groups. The control circuitry is connected to the bitcell groups via the bitlines. The control circuitry adjusts connections with the bitcell groups to include a first bitcell group of the bitcell groups in memory operations and exclude a second bitcell group of the bitcell groups from the memory operations based on a half-word control signal being enabled.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.