System and method for SEU detection and correction
US12346226B2 · kind B2 · utility
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8References
20Claims
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Key dates
| Filing date | Oct 4, 2023 |
| Grant date | Jul 1, 2025 |
| Priority date | — |
| Expiry date | Oct 4, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1608
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments herein describe a circuit for detecting a single event upset (SEU). The circuit includes a latch including an output node, a first parity node, and a second parity node and correction circuitry configured to correct a single event upset (SEU) at the output node using the first and second parity nodes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.