Method and wafer processing furnace for forming an epitaxial stack on a plurality of substrates

US12362174B2 · kind B2 · utility

Assignee

• ASM IP Holding B.V. · NL

Inventors

• Steven R. A. Van Aerde · Tielt-Winge, BE
• Wilco Verweij · Nijkerk, NL
• Bert Jongbloed · Oud-Heverlee, BE
• Dieter Pierreux · Dilbeek, BE
• Kelly Houben · Sint-Bernard, BE
• Rami Khazaka · Antibes, FR
• Frederick Aryeetey · Phoenix, US
• Peter Westrom · Phoenix, US
• Omar Elleuch · Litchfield Park, US
• Caleb Miskin · Mesa, US

Key dates

• Filing date: Jan 11, 2023
• Grant date: Jul 15, 2025
• Expiry date: Jun 18, 2043

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/0262
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A method and a wafer processing furnace for forming an epitaxial stack on a plurality of substrates is provided. In a preferred embodiment, the method comprises providing the plurality of substrates to a process chamber. A plurality of deposition cycles is executed, thereby forming the epitaxial stack on the plurality of substrates. The epitaxial stack comprises a plurality of epitaxial pairs, wherein the epitaxial pairs each comprises a first epitaxial layer and a second epitaxial layer, the second epitaxial layer being different from the first epitaxial layer. Each deposition cycle comprises a first deposition pulse and a second deposition pulse. The first deposition pulse comprises a provision of a first reaction gas mixture to the process chamber, thereby forming the first epitaxial layer. The second deposition pulse comprises a provision of a second reaction gas mixture to the process chamber, thereby forming the second epitaxial layer. The first deposition pulse or the second deposition pulse further comprises a provision of a dopant precursor gas to the process chamber.