Area, cost, and time-effective scan coverage improvement
US12366605B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 24, 2023 |
| Grant date | Jul 22, 2025 |
| Priority date | — |
| Expiry date | Jun 9, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/3187
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
According to an embodiment, a digital circuit includes an OR gate and a flip-flop. The OR gate includes a first input and a second input. The first input of the OR gate is coupled to a control signal, and the second input of the OR gate is coupled to an uncovered functional combination logic of the digital circuit. The first input of the OR gate is configured to be pulled low by the control signal in response to setting the digital circuit in a configuration to test the uncovered functional combination logic. The flip-flop includes a reset pin or a set pin coupled to the output of the OR gate. The output of the flip-flop is configured to be observed during a testing of the uncovered functional combination logic to detect defects in the digital circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.