Nanosheet transistor
US12369379B2 · kind B2 · utility
0Cited by
10References
20Claims
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Assignee
Inventors
Key dates
| Filing date | Dec 27, 2023 |
| Grant date | Jul 22, 2025 |
| Priority date | — |
| Expiry date | Dec 27, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/018
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Inner and outer spacers for nanosheet transistors are formed using techniques that improve junction uniformity. One nanosheet transistor device includes outer spacers and an interlevel dielectric layer liner made from the same material. A second nanosheet transistor device includes outer spacers, inner spacers and an interlevel dielectric layer liner that are all made from the same material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.