FinFET devices

US12376369B2 · kind B2 · utility

Assignee

• Adeia Semiconductor Solutions LLC · US

Inventors

• Veeraraghavan S. Basker · Schenectady, US
• Kangguo Cheng · Schenectady, US
• Theodorus E. Standaert · Clifton Park, US
• Junli Wang · Slingerlands, US

Key dates

• Filing date: Feb 28, 2023
• Grant date: Jul 29, 2025
• Expiry date: Feb 28, 2043

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/834
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

FinFET devices and processes to prevent fin or gate collapse (e.g., flopover) in finFET devices are provided. The method includes forming a first set of trenches in a semiconductor material and filling the first set of trenches with insulator material. The method further includes forming a second set of trenches in the semiconductor material, alternating with the first set of trenches that are filled. The second set of trenches form semiconductor structures which have a dimension of fin structures. The method further includes filling the second set of trenches with insulator material. The method further includes recessing the insulator material within the first set of trenches and the second set of trenches to form the fin structures.