Transistors with multiple silicide layers
US12389616B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Feb 11, 2022 |
| Grant date | Aug 12, 2025 |
| Priority date | — |
| Expiry date | Dec 17, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/792
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Structures for a transistor and methods of forming a structure for a transistor. The structure includes a first dielectric spacer, a second dielectric spacer, and a gate laterally between the first dielectric spacer and the second dielectric spacer. The gate includes a first silicide layer extending from the first dielectric spacer to the second dielectric spacer. The structure further includes a second silicide layer within the first silicide layer, and a contact that is aligned to the second silicide layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.