Backend memory with air gaps in upper metal layers

US12396155B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Abhishek A. Sharma · Hillsboro, US
• Albert Chen · Portland, US
• Wilfred Gomes · Portland, US
• Fatih Hamzaoglu · Portland, US
• Travis W. Lajoie · Forest Grove, US
• Van H. Le · Portland, US
• Alekhya Nimmagadda · Hillsboro, US
• Miriam Reshotko · Portland, US
• Hui Jae Yoo · Hillsboro, US

Key dates

• Filing date: Jun 18, 2021
• Grant date: Aug 19, 2025
• Expiry date: Dec 20, 2043

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D88/00
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

An example IC device includes a frontend layer and a backend layer with a metallization stack. The metallization stack includes a backend memory layer with a plurality of memory cells with backend transistors, and a layer with a plurality of conductive interconnects (e.g., a plurality of conductive lines) and air gaps between adjacent ones of the plurality of interconnects. Providing air gaps in upper metal layers of metallization stacks of IC devices may advantageously reduce parasitic effects in the IC devices because such effects are typically proportional to the dielectric constant of a surrounding medium. In turn, reduction in the parasitic effects may lead to improvements in performance of, or requirements placed on, the backend memory.