Gate all around device with fully-depleted silicon-on-insulator
US12402351B2 · kind B2 · utility
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12Claims
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Key dates
| Filing date | Jan 25, 2022 |
| Grant date | Aug 26, 2025 |
| Priority date | — |
| Expiry date | Apr 22, 2043 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S977/938
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
Horizontal gate-all-around devices and methods of manufacturing are described. The hGAA devices include a fully-depleted silicon-on-insulator (FD-SOI) under the channel layers in the same footprint as the hGAA. The buried dielectric insulating layer of the FD-SOI includes one or more of silicon oxide (SiOx), silicon nitride (SiN), silicon carbide (SiC), and a high-k material, and the buried dielectric insulating layer has a thickness in a range of from 0 nm to 10 nm.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.