Dynamic latches above a three-dimensional non-volatile memory array
US12406731B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 24, 2023 |
| Grant date | Sep 2, 2025 |
| Priority date | — |
| Expiry date | Mar 6, 2044 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3459
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Control logic in a memory device causes a pass voltage to be applied to a plurality of wordlines of a block of a memory array of the memory device, the block comprising a plurality of sub-blocks, and the pass voltage to boost a channel potential of each of the plurality of sub-blocks to a boost voltage. The control logic further selectively discharges the boost voltage from one or more of the plurality of sub-blocks according to a data pattern representing a sequence of bits to be programmed to respective memory cells of the plurality of sub-blocks. In addition, the control logic causes a single programming pulse to be applied to a selected wordline of the plurality of wordlines of the block to program the respective memory cells of the plurality of sub-blocks according to the data pattern.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.