Bilayer memory stacking with computer logic circuits shared between bottom and top memory layers

US12406956B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Abhishek A. Sharma · Hillsboro, US
• Van H. Le · Portland, US
• Kimin Jun · Hillsboro, US
• Wilfred Gomes · Portland, US
• Hui Jae Yoo · Hillsboro, US

Key dates

• Filing date: Aug 31, 2021
• Grant date: Sep 2, 2025
• Expiry date: Jan 4, 2044

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/1436
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Integrated circuit (IC) devices implementing bilayer memory stacking with compute logic circuits shared between bottom and top memory layers are disclosed. An example IC device includes a first IC structure that includes one or more memory layers but not necessarily compute logic circuits, the first IC structure being bonded with a second IC structure that includes at least one layer of compute logic circuits and further includes one or more memory layers stacked above the compute logic circuits. The first and second IC structures may be bonded so that the compute logic circuits of the second IC structure may be communicatively coupled to memory layers of both the first and second IC structures.