Device comprising spacers including a localised airgap and associated manufacturing methods
US12408405B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 14, 2022 |
| Grant date | Sep 2, 2025 |
| Priority date | — |
| Expiry date | Jan 6, 2044 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76283
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
A semiconductor device made on a substrate including an active region and a non-active region at least partially surrounding the active region, a plurality of gate stacks, a part of each gate stack being on the active region, each gate stack being separated from adjacent gate stacks by a spacer by a distance e, the device being such that, for each gate stack, the part of the gate stack located on the active region has a height h2, the part of the same gate stack located on the non-active region has a height h1, and h2/e=a2 and h1/e=a1<alim where a2 is an aspect ratio such that, upon growth of the spacer material forming the spacers, an airgap is in the spacer, and a1 is an aspect ratio such that, upon growth of the spacer material forming the spacers, no airgap is in the spacer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.