Time decoupled write operations for non-linear polar material based memory

US12412611B1 · kind B1 · utility

Assignee

• Kepler Computing Inc. · US

Inventors

• Rajeev Kumar Dokania · Beaverton, US
• Pramod Kolar · Cary, US
• Mustansir Yunus Mukadam · Seattle, US
• Darshak Doshi · Sunnyvale, US
• Biswajeet Guha · Hillsboro, US
• Tanay Gosavi · Portland, US
• Amrita Mathuriya · Portland, US
• Debo Olaosebikan · San Francisco, US
• Sasikanth Manipatruni · Ithaca, US

Key dates

• Filing date: Apr 28, 2023
• Grant date: Sep 9, 2025
• Expiry date: Sep 9, 2043

Classification

• Technology area (CPC G): Physics
• CPC primary: G11C11/2297
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

Described herein is a read and write scheme to improve memory reliability. In at least one embodiment, one or more circuitries are provided to perform logic 0 write operation in a first phase and logic 1 write operation in a second phase for a plurality of bit-cells controlled by a word-line. In at least one embodiment, an individual bit-cell comprises a transistor having a gate terminal coupled to the word-line; and a capacitor including non-linear polar material, wherein the capacitor has a first terminal coupled to a plate-line and a second terminal coupled to the transistor, wherein a source or drain terminal of the transistor is coupled to a bit-line.