Semiconductor packages and methods of forming the same
US12412824B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 13, 2023 |
| Grant date | Sep 9, 2025 |
| Priority date | — |
| Expiry date | Mar 16, 2044 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/182
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package, comprising: a first redistribution structure including a first redistribution via; a first package that is on an upper surface of the first redistribution structure and comprises a first pad; a second redistribution structure that is on a lower surface of the first redistribution structure and comprises a second redistribution via; a second semiconductor chip that is between the first redistribution structure and the second redistribution structure and comprises a connection pad; and a vertical connection structure that is between the first redistribution structure and the second redistribution structure, wherein the vertical connection structure is electrically connected to the first redistribution via and the second redistribution via, the connection pad is electrically connected to the second redistribution via, and the first redistribution via is electrically connected to the first pad.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.