Microelectronics package comprising a package-on-package (PoP) architecture with inkjet barrier material for controlling bondline thickness and PoP adhesive keep out zone

US12417958B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Elizabeth Nofen · Gilbert, US
• Shripad Gokhale · Gilbert, US
• Nick Ross · San Francisco, US
• Amram Eitan · Scottsdale, US
• Nisha Ananthakrishnan · Chandler, US
• Robert M. Nickerson · Chandler, US
• Purushotham Kaushik Muthur Srinath · Chandler, US
• Yang Guo · Nanhu, CN
• John C. DECKER · Tempe, US
• Hsin-Yu Li · Lexington, US

Key dates

• Filing date: Dec 28, 2023
• Grant date: Sep 16, 2025
• Expiry date: Dec 28, 2043

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/181
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a first package, wherein the first package comprises, a first package substrate, a first die over the first package substrate, a first mold layer over the first package substrate and around the first die, and a plurality of through mold interconnects (TMIs) through the first mold layer. The electronic package may further comprise a second package electrically coupled the first package by the TMIs, wherein the second package comprises a second package substrate, a second die over the second package substrate, and a solder resist over a surface of the second package substrate opposite from the second die. In an embodiment, the electronic package may also comprise a barrier between the first package and the second package.