Semiconductor packages using package in package systems and related methods
US12417999B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Apr 11, 2024 |
| Grant date | Sep 16, 2025 |
| Priority date | — |
| Expiry date | Apr 11, 2044 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/1815
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Implementations of a semiconductor package may include two or more die, each of the two more die coupled to a metal layer at a drain of each of the two more die, the two or more die and each metal layer arranged in two parallel planes; a first interconnect layer coupled at a source of each of the two more die; a second interconnect layer coupled to a gate of each of the two or more die and to a gate package contact through one or more vias; and an encapsulant that encapsulates the two or more die and at least a portion of the first interconnect layer, each metal layer, and the second interconnect layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.