Buried power rails integrated with decoupling capacitance

US12431424B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Bernd Waidhas · Nittendorf, DE
• Harald Gossner · Riemerling, DE
• Wolfgang Molzer · Ottobrunn, DE
• Georg Seidemann · Landshut, DE
• Michael Langenbuch · Munich, DE
• Martin Ostermayr · Straubing, DE
• Joachim Singer · Neubiberg, DE
• Thomas Wagner · Regelsbach, DE
• Klaus Herold · Poughquag, US

Key dates

• Filing date: Dec 17, 2021
• Grant date: Sep 30, 2025
• Expiry date: Jan 30, 2044

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/834
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

IC devices including BPRs with integrated decoupling capacitance are disclosed. An example IC device includes a first layer comprising a transistor and a support structure adjoining the first layer. The support structure includes BPRs, which are power rails buried in the support structure, and a decoupling capacitor based on the BPRs. The conductive cores of the BPRs are the electrodes of the decoupling capacitor. The dielectric barriers of the BPRs can be the dielectric of the decupling capacitor. The dielectric of the decupling capacitor may also include a dielectric element between the BPRs. Additionally or alternatively, the IC device includes another decoupling capacitor at the backside of the support structure. The other decoupling capacitor is coupled to the BPRs and can provide additional decoupling capacitance for stabilizing power supply facilitated by the BPRs.