Process for formation of trench in integrated circuit structure using isotropic and anisotropic etching
US4639288A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 5, 1984 |
| Grant date | Jan 27, 1987 |
| Priority date | — |
| Expiry date | Nov 5, 2004 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/763
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An improved process is disclosed for making an integrated circuit structure wherein a trench is etched into one or more layers to electrically separate one of the devices in the integrated circuit structure from other portions thereof by first patterning silicon dioxide and silicon nitride layer on a layer of silicon. The improvement comprises isotropically etching the silicon layer to provide an enlarged shallow etch area undercutting the patterned silicon dioxide and silicon nitride layers. Subsequent deeper anisotropic etching to form the trench will result in a trench having an enlarged upper width which, in turn, prevents the formation of voids adjacent the upper portion of the trench during subsequent oxidation and polysilicon deposition steps. Possible creation of openings to such voids in the polysilicon during subsequent planarization is thereby eliminated thus avoiding undesirable oxidation of such voids and undesirable stress formation therefrom.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.