Buried-resistance semiconductor device and fabrication process
US4663647A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 23, 1985 |
| Grant date | May 5, 1987 |
| Priority date | — |
| Expiry date | Sep 23, 2005 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/761
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A buried-resistance semiconductor device is constructed by forming a P-type monocrystalline silicon substrate on which an epitaxial layer of silicon doped with type N impurities is grown, a portion of the epitaxial layer being insulated by a P-type insulating region extending from the substrate to the surface of the epitaxial layer. Two suitably-spaced terminals are secured to the surface of the epitaxial layer in the area bounded by the insulating region. Two separation regions extending into the surface layer are formed in the part of the epitaxial layer between the terminals, and a buried region extends from the substrate between the separation regions without being in contact with them. The three regions are of P-type material, and have an elongated shape and are bounded at the ends by the insulating region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.