Power transistor with spaced subtransistors having individual collectors

US4682197A · kind A · utility

Assignee

• SGS Microelettronica S.p.A. · IT

Inventors

• Flavio Villa · Milano, IT
• Bruno Murari · Monza, IT
• Franco Bertotti · Milano, IT
• Aldo Torazzina · Lissone, IT
• Fabrizio Stefani · Varese, IT

Key dates

• Filing date: Dec 23, 1985
• Grant date: Jul 21, 1987
• Expiry date: Dec 23, 2005

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B20/10

Abstract

This integrated semiconductor device aims at drastic reduction of the direct secondary breakdown phenomena and has a plurality of side-by-side elementary transistors forming an interdigited structure. To reduce the thermal interaction between the elementary transistors, the latter are spaced apart from one another by a distance approximately equal to the width of one elementary transistor and are driven by current sources. Spacing apart reduces electrothermal interaction. Further, in order to minimize the device area requirements, the space between any two adjacent elementary transistors is made to accommodate drive transistors operating as current sources, or the elementary transistors of the complementary stage where the device forms a class B output stage, the two output transistors whereof are alternatively switched on.