Via in a planarized dielectric and process for producing same
US4789760A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 30, 1985 |
| Grant date | Dec 6, 1988 |
| Priority date | — |
| Expiry date | Apr 30, 2005 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76877
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An improved integrated circuit structure is disclosed wherein a first metal layer is coated with a dielectric material and another metal layer is applied over the dielectric layer and a via electrically interconnects at least a portion of the first metal layer with at least a portion of the second metal layer. The via is formed having a lower first width dimension adjacent the first metal layer and an upper enlarged width portion adjacent the second metal layer formed by masking the dielectric with a mask having an opening conforming to the first dimension and isotropically etching the dielectric through the mask to provide the enlarged portion adjacent the upper surface of the dielectric.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.