Dynamic random access memory having buried word lines
US4873560A · kind A · utility
37Cited by
3References
42Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 16, 1988 |
| Grant date | Oct 10, 1989 |
| Priority date | — |
| Expiry date | Feb 16, 2008 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/922
Abstract
This invention relates to a very large scale dynamic random access memory, and discloses a memory cell having a reduced step on the device surface portion and being hardly affected by incident radioactive rays. In a semiconductor memory consisting of a deep hole bored in a semiconductor substrate, a capacitor formed on the sidewall portion at the lower half of the deep hole and a switching transistor formed immediately above the capacitor, at least the half of a word line constituting the gate of the switching transistor is buried in an elongated recess formed at the surface portion of the semiconductor substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.