Dynamic random access memory having a trench capacitor
US4894696A · kind A · utility
54Cited by
9References
30Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 8, 1986 |
| Grant date | Jan 16, 1990 |
| Priority date | — |
| Expiry date | Dec 8, 2006 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/90
Abstract
A very highly integrated semiconductor memory which enables the dynamic random access memory to develop less soft error and to eliminate margin for aligning the masks, that hinders the device from being highly integrated. The memory cell capacitor is constituted by a trench which is provided at a position defined by an insulator formed on the side of gate electrode of a MOS transistor that constitutes the memory cell. Therefore, the MOS transistor and the trench capacitor are self-aligned, and no margin is required for alignment.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.