Electrically erasable programmable read-only memory with NAND cell structure that suppresses memory cell threshold voltage variation
US4939690A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 27, 1988 |
| Grant date | Jul 3, 1990 |
| Priority date | — |
| Expiry date | Dec 27, 2008 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0483
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An erasable programmable read-only memory with NAND cell structure is disclosed which includes NAND cell blocks each of which has a selection transistor connected to a corresponding bit line and a series array of memory cell transistors. Each cell transistor has a floating gate and a control gate. Word lines are connected to the control gates of the cell transistors. In a data erase mode all the memory cells are simultaneously erased by applying a "H" level potential to the control gates of the memory cells and a "L" level potential to the bit lines. Prior to such a simultaneous erase, charges are removed from charge accumulation layers of the memory cells so that the threshold values of the memory cells are initialized. The threshold initialization is performed on the series-arrayed memory cell transistors in the NAND cell block in sequence.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.