Semiconductor memory having stacked capacitor
US5012310A · kind A · utility
16Cited by
6References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 13, 1990 |
| Grant date | Apr 30, 1991 |
| Priority date | — |
| Expiry date | Aug 13, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/31
Abstract
A megabit dynamic random access memory realizing high integration and high reliability is disclosed. The need for an allowance for photomask alignment which is carried out to produce a stacked capacitor memory cell is eliminated. The plate electrode of each memory cell is isolated from the corresponding data line in a memory array by means of an insulating film which is self-alignedly provided around the plate electrode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.