Flash EEPROM array with negative gate voltage erase operation
US5077691A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 23, 1989 |
| Grant date | Dec 31, 1991 |
| Priority date | — |
| Expiry date | Oct 23, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/5006
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A flash EEPROM cell array is erased by applying a zero reference voltage to the bulk substrate of the cell, a relatively high negative voltage to the control gate of the cell and a relatively low positive voltage to the source region of the cell. Because of a relatively low reverse voltage developed between the source region of the cell and the bulk substrate, the generation of hot holes is inhibited and improved performance may be obtained. The source region is preferably single diffused rather than double-diffused so that the cell can occupy a minimum area for a given design rule. The low positive voltage applied to the source is preferably less than or equal to the voltage, V.sub.CC presented at a +5V chip power supply pin. This makes it possible for the +5V pin to directly supply source current during erasure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.