High performance vertical bipolar transistor structure via self-aligning processing techniques
US5128271A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 2, 1990 |
| Grant date | Jul 7, 1992 |
| Priority date | — |
| Expiry date | Nov 2, 2010 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/05
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention is a self-aligned, vertical bipolar transistor structure and a method of manufacturing such a structure. Reducing lateral dimensions with optical lithography is difficult and not much is gained without concurrently reducing alignment tolerances. For bipolar transistors the alignment tolerance is particularly important since it determines the parasitic capacitances and resistances and thus directly affects speed. In this application a new fully self-aligned transistor structure is presented that self-aligns the shallow trench, extrinsic base contact, and the emitter polysilicon to the intrinsic device area. The structure has no critical alignments. To insure extrinsic-intrinsic base linkup the intrinsic base is put in early in the process, conserved during the stack etch, and patterned underneath the sidewall during the silicon mesa etch. Unlike other mesa-like transistor structures, no out-diffusion of the extrinsic-base is required and therefore low-temperature processing can be used to maintain a narrow vertical profile.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.