Semiconductor memory device
US5148255A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 23, 1991 |
| Grant date | Sep 15, 1992 |
| Priority date | — |
| Expiry date | Jan 23, 2011 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/213
Abstract
Disclosed is a semiconductor device, such as a semiconductor memory device, having structure wherein invasion of minority carriers from the semiconductor substrate into components of the device, formed on the substrate, can be avoided. The semiconductor memory device can be an SRAM or DRAM, for example, and includes a memory array and peripheral circuit on a substrate. In one aspect of the present invention, a buried layer of the same conductivity type as that of the substrate, but with a higher impurity concentration than that of the substrate, is provided beneath at least one of the peripheral circuit and memory array. A further region can extend from the buried layer, for example, to the surface of the semiconductor substrate, the buried layer and further region in combination acting as a shield to prevent minority carriers from penetrating to the device elements. As a second aspect of the present invention, first carrier absorbing areas (to absorb minority carriers) are located between the memory array and the switching circuit of the peripheral circuit, and second carrier absorbing areas are provided to surround input protective elements of the device. As a third embodiment of…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.