Packaging for a semiconductor die
US5155067A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 26, 1991 |
| Grant date | Oct 13, 1992 |
| Priority date | — |
| Expiry date | Mar 26, 2011 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/09701
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Disclosed is a means for packaging a plurality of semiconductor die into one component. Present designs comprise multiple singulated unpackaged die which have been probed, but not rigorously tested for complete functionality and adherence to required operating specifications. The yields of present designs of multi-chip modules (MCMs) are low and functional units are therefore costly. Unlike present designs incorporating multiple die, the inventive design comprises devices which have been singulated, packaged, and thoroughly tested for functionality and adherence to required specifications. A plurality of packaged devices are then received by a housing. The conductive leads of the packaged devices are electrically coupled with pads manufactured into the housing. These pads are enjoined with traces within the housing, which terminate externally to the housing. Input/output leads are then electrically coupled with the traces, or are coupled with the traces as the housing is manufactured. The I/O leads provide means for connection of the housing with the electronic device into which it is installed. A lid received by the housing hermetically seals the packaged die in the housing, and p…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.