Dynamic random access memory having trench capacitors and vertical transistors
US5177576A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 6, 1991 |
| Grant date | Jan 5, 1993 |
| Priority date | — |
| Expiry date | May 6, 2011 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/395
Abstract
A vertical semiconductor memory device is provided which capable of miniaturization. More particularly, a memory cell is provided having a trench capacitor and a vertical transistor in a dynamic random access memory suitable for high density integration. An object of this arrangement is to provide a vertical memory cell capable of miniaturization for use in a ultra-high density integration DRAM of a Gbit class. This memory cell is characterized in that each memory cell is covered with an oxide film, an impurity area does not exist on the substrate side, an area in which a channel area is formed is a hollow cylindrical single crystal area, connection of impurity areas as source-drain areas and bit lines and the electrode of a capacitor is made by self-alignment and connection between a word line electrode and a gate electrode is also made by self-alignment.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.