Selective plating method for forming integral via and wiring layers
US5209817A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 22, 1991 |
| Grant date | May 11, 1993 |
| Priority date | — |
| Expiry date | Aug 22, 2011 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2203/072
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
In a multi-level wiring structure wires and vias are formed by an isotropic deposition of a conductive material, such as copper, on a dielectric base, such as a polyimide. In a preferred embodiment of the invention copper is electroplated to a thin seed conducting layer deposited on the surface of the dielectric base in which via openings have been formed. Openings in a resist formed on the surface of the dielectric base over the seed layer forms a pattern defining the wiring and via conductor features. Electroplated copper fills the via openings and wire pattern openings in the resist isotropically so that the upper surfaces of the wiring and vias are co-planar when the plating step is complete. In adding subsequent wiring levels, the resist is removed and the via conductor and wiring pattern covered with another dielectric layer which both encapsulates the conductors of the previous layer and serves as the base for the next level which is formed in the same manner as the previous level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.