High-frequency semiconductor wafer processing method using a negative self-bias
US5223457A · kind A · utility
78Cited by
8References
6Claims
0Family size
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Key dates
| Filing date | Oct 11, 1991 |
| Grant date | Jun 29, 1993 |
| Priority date | — |
| Expiry date | Oct 11, 2011 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/051
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A plasma process apparatus capable of operation significantly above 13.56 MHz can produce reduced self-bias voltage of the powered electrode to enable softer processes that do not damage thin layers that are increasingly becoming common in high speed and high density integrated circuits. A nonconventional match network is used to enable elimination of reflections at these higher frequencies. Automatic control of match network components enables the rf frequency to be adjusted to ignite the plasma and then to operate at a variable frequency selected to minimize process time without significant damage to the integrated circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.