Method for producing gate overlapped lightly doped drain (GOLDD) structure for submicron transistor

US5227320A · kind A · utility

Assignee

• VLSI Technology, Inc. · US

Inventors

• Eric A. Johnson · Hudson, US
• Ying-Tsong Loh · Saratoga, US
• Yoshiko H. Strunk · Sunnyvale, US
• Chung S. Wang · Fremont, US

Key dates

• Filing date: Sep 10, 1991
• Grant date: Jul 13, 1993
• Expiry date: Sep 10, 2011

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/605

Abstract

A method produces a transistor with an overlapping gate. A first gate region is placed on a substrate between two source/drain regions. The first gate region includes a polysilicon region on top of a dielectric region. Gate overlap regions are placed around the polysilicon region. The gate overlap regions extend out over the two source/drain regions. The gate overlap regions are formed of a metal-silicide layer, for example Titanium-silicide. A top portion of the metal-silicide layer is oxidized to form a silicon dioxide layer on top of the metal-silicide layer. At the time of oxidation, the metal-silicide layer is also annealed to which further helps to improves the Titanium-silicide stoichiometry.