Circuit for synchronizing refresh cycles in self-refreshing drams having timing circuit shutdown
US5229970A · kind A · utility
30Cited by
11References
49Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 15, 1991 |
| Grant date | Jul 20, 1993 |
| Priority date | — |
| Expiry date | Apr 15, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/406
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The invention is a circuit synchronizing the refresh cycles of a bank of self-refreshing DRAMs. The refresh cycles are synchronized through a bidirectional control path from each self-refreshing DRAM to its respective external refresh pin. An arbitration circuit determines the self-refreshing DRAM having a fastest timing sequence, maintains that timing sequence and shuts down all timing circuits having slower timing sequences. The arbitration circuit of each self-refreshing DRAM provides a refresh signal to each respective refresh circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.