Offset magnetoresistive memory structures
US5251170A · kind A · utility
62Cited by
10References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 4, 1991 |
| Grant date | Oct 5, 1993 |
| Priority date | — |
| Expiry date | Nov 4, 2011 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N50/10
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A digital memory having a plurality of electrically connected bit structures extending over a path with adjacent ones offset from one another in a direction substantially perpendicular to that path. The bit structures are formed of two ferromagnetic films with an exchange coupling barrier therebetween.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.