Method to eliminate gate filaments on field plate isolated devices
US5252506A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 5, 1992 |
| Grant date | Oct 12, 1993 |
| Priority date | — |
| Expiry date | May 5, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/038
Abstract
A method is disclosed for preventing formation of undesirable polysilicon word line gate filaments in integrated circuit devices such as VLSI dynamic random access memories employing field plate isolation. Before the word lines are processed, an oxide layer is formed in the field plate openings beneath sidewalls of nitride along the edges of the field plate openings. The oxide layer partially fills an undercut area beneath a dip out of the sidewall of nitride. The dip out of the sidewall of nitride is removed. The removal of the dip out and the partial filling of the undercut area reduces the possibility of polysilicon word line filaments from forming around the edge of the field plate openings in the undercut area when the word lines are later added. A field plate isolated memory device is also disclosed wherein along the edges of the field plate openings, the partially filling oxide layer and the sidewall nitride layer are approximately coincident.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.