Trenched DMOS transistor fabrication using six masks
US5316959A · kind A · utility
87Cited by
1References
8Claims
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Assignee
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Key dates
| Filing date | Aug 12, 1992 |
| Grant date | May 31, 1994 |
| Priority date | — |
| Expiry date | Aug 12, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/106
Abstract
A trenched DMOS transistor is fabricated using six masking steps. One masking step defines both the P+ regions and the active portions of the transistor which are masked using a LOCOS process. The LOCOS process also eliminates the poly stringer problem present in prior art structures by reducing the oxide step height. A transistor termination structure includes several field rings, each set of adjacent field rings separated by an insulated trench, thus allowing the field rings to be spaced very close together. The field rings and trenches are fabricated in the same steps as are corresponding portions of the active transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.