Forming resistors for intergrated circuits

US5316978A · kind A · utility

Assignee

• Nortel Networks Limited · CA

Inventors

• John M. Boyd · Atascadero, US
• Joseph P. Ellul · Ottawa, CA
• Sing-Pin Tay · Ottawa, CA

Key dates

• Filing date: Mar 25, 1993
• Grant date: May 31, 1994
• Expiry date: Mar 25, 2013

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y10S148/136

Abstract

A method is provided for forming multi-valued linear resistors for an integrated circuit using a single mask level. A plurality of trenches are defined in a substrate. Each trench has contact regions of a specific lateral dimension and a narrower portion extending therebetween. Successive conformal layers of a first dielectric layer, a first conductive layer of high resistivity and a second conductive layer of lower resistivity are provided to fill the trench. The amount of the second conductive layer which fills the trench depends on the width of the trench. The resulting structure is planarized, preferably by chemical-mechanical polishing to provide fully planarized topography. Advantageously when the first and second conductive layers are provided from layers of undoped and doped polysilicon respectively, the trench dimensions control the amount of dopant incorporated in each region of the trench. After annealing to diffuse dopant, the wider end contact regions are heavily doped to form contact regions, and the intermediate narrow portion of the trench is doped to a level dependent on the width of the trench, thereby forming a resistive element having a resistivity inversely dep…