Flash EEPROM array with high endurance
US5335198A · kind A · utility
157Cited by
4References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 6, 1993 |
| Grant date | Aug 2, 1994 |
| Priority date | — |
| Expiry date | May 6, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/5006
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An over-erased bit correction structure is provided for performing a correction operation on over-erased memory cells in an array of flash EEPROM memory cells during programming operations so as to render high endurance. Sensing circuitry (23) is used to detect column leakage current indicative of an over-erased bit. If an over-erased bit is determined, a pulse counter (25) is activated so as to apply programming pulses to the control gate of the selected memory cell so as to program back the negative threshold voltage of the over-erased bit to a positive voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.