Stacked-layer structure polysilicon emitter contacted p-n junction diode
US5347161A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 2, 1992 |
| Grant date | Sep 13, 1994 |
| Priority date | — |
| Expiry date | Sep 2, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/62
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A process is used to fabricate diodes having an emitter contacted p-n junction. A stack of n.sup.+ -type polysilicon layers are formed one upon the other upon a p-type silicon substrate. In an accordingly fabricated diode, native oxide layers that forms between the n.sup.+ -type polysilicon layer and the p-type substrate would be liable to be broken up, and thicker epitaxial layer would be formed between the same. The p-n junction is with a thickness of 0.05-0.2 .mu.m. As the diode is reverse-biased, for example at -5V, leakage current could be less than 1 n.ANG./cm.sup.2. The reverse-bias breakdown voltage could be larger than -100 V. When forward-biased, the ideality factor of the diode is close to unity.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.