Semiconductor memory device for performing parallel operations on hierarchical data lines
US5386394A · kind A · utility
32Cited by
7References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 2, 1993 |
| Grant date | Jan 31, 1995 |
| Priority date | — |
| Expiry date | Sep 2, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1006
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The semiconductor device has more-significant global data lines and less-significant data lines hierarchically formed, and switches for controlling the more-significant global data lines and the less-significant data lines to be connected each other. In addition, the semiconductor device has the unit for precharging the global data lines independently of the data lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.