Simple planarized trench isolation and field oxide formation using poly-silicon
US5411913A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 29, 1994 |
| Grant date | May 2, 1995 |
| Priority date | — |
| Expiry date | Apr 29, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/763
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A device isolation scheme that is particularly suited to the fabrication of high density, high performance CMOS, bipolar, or BiCMOS devices, and overcomes many of the problems associated with existing isolation methods. Photolithographic techniques are used to define active regions on a substrate. Using the photoresist as a mask for the active regions, the silicon in the inactive regions is etched. A pad oxide layer and nitride layer are then formed on the substrate. A layer of oxide is then deposited and photolithographic techniques are again used to define the locations for desired trench structures. After removal of the remaining photoresist, deep trenches are etched in the silicon substrate. An oxidation step is then carried out to provide a layer of oxide lining the trenches, followed by deposition of a layer of poly-silicon over the substrate, filling the trenches. The poly-silicon layer is etched back, removing it from the tops of the trenches and the field regions, and leaving a poly-silicon spacer on the sides of those portions of the previously deposited oxide layer which cover the active regions. The spacers are used to align a photoresist mask which is used to etch away…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.