Method of surface protection of a semiconductor wafer during polishing
US5424224A · kind A · utility
18Cited by
4References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 19, 1993 |
| Grant date | Jun 13, 1995 |
| Priority date | — |
| Expiry date | Jan 19, 2013 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/959
- WIPO fieldMachine tools
- WIPO sectorMechanical engineering
Abstract
The protection to the backside of the semiconductor wafer is accomplished by applying a layer of silicon oxide or silicon nitride or other deposited material to the back surface of a semiconductor wafer to protect against particles, scratches, and etching by mild caustic solutions. The layer remains in place during all three processes, edge pre-polish, mirror edge polish, and wafer polish.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.