Method of fabricating a textured tunnel oxide for EEPROM applications
US5429966A · kind A · utility
47Cited by
4References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 22, 1993 |
| Grant date | Jul 4, 1995 |
| Priority date | — |
| Expiry date | Jul 22, 2013 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/964
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Disclosed is a thin textured tunnel oxide prepared by thermal oxidation of a thin polysilicon film on Si substrate. Due to the rapid diffusion of oxygen through grain boundries of the thin polysilicon film into the Si substrate and the enhanced oxidation rate at grain boundries, a textured Si/SiO.sub.2 interface is obtained. The textured Si/SiO.sub.2 interface results in localized high fields and causes a much higher electron injection rate. EEPROM memory cells having the textured Si/SiO.sub.2 exhibit a lower electron trapping rate and a lower interface state generation rate even under high field operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.