Multi-step chemical vapor deposition method for thin film transistors
US5441768A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 8, 1994 |
| Grant date | Aug 15, 1995 |
| Priority date | — |
| Expiry date | Feb 8, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/0321
- WIPO fieldSurface technology, coating
- WIPO sectorChemistry
Abstract
An improved method of depositing films of a gate silicon nitride and an amorphous silicon on a thin film transistor substrate at high deposition rates while maintaining superior film quality is provided. The material near the interface between the amorphous silicon and the nitride are deposited at a low deposition rate which produces superior quality films. The region away from the interface are deposited at a high deposition rate which produces lesser, but still good quality films. By using this method, superior quality thin film transistors can be produced at very high efficiency. The method can be carried out by depositing a high quality g-SiN.sub.x at a low deposition rate on top of an average quality gate nitride deposited at a high deposition rate and then depositing an amorphous silicon layer. It also applies in a process where high quality amorphous silicon is first deposited at a low deposition rate on a gate nitride layer to form an interface, and then average quality amorphous silicon is deposited at a high deposition rate to complete the silicon layer. The unique process can be applied whenever an interface exists with an active semiconductor layer of amorphous silicon.…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.