Method for manufacturing semiconductor integrated circuit device having a fuse element
US5444012A · kind A · utility
Assignees
Inventors
Key dates
| Filing date | Jul 20, 1994 |
| Grant date | Aug 22, 1995 |
| Priority date | — |
| Expiry date | Jul 20, 2014 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/055
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In depositing a silicon oxide film which constitutes part of a final passivation film onto a bonding pad formed on an interlayer insulating film, the silicon oxide depositing step is divided in two stages, and after the first deposition, the bonding pad is once exposed by etching, then the second deposition is performed, whereby the silicon oxide film which has thus been deposited in two stages is formed over a fuse element formed under the interlayer insulating film, while on the bonding pad is formed only the silicon oxide film deposited in the second stage. As a result, at the time of etching polyimide resin, silicon nitride film and silicon oxide film successively to expose the bonding pad, there remains a sufficient thickness of insulating film between the bottom of an aperture which is formed at the same time and the fuse element. Thereafter, an electrical test is conducted while applying a probe to the bonding pad and, where required, the fuse element located under the aperture is cut.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.