Process for forming stable local interconnect/active area silicide structure VLSI applications
US5451545A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 21, 1994 |
| Grant date | Sep 19, 1995 |
| Priority date | — |
| Expiry date | Sep 21, 2014 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/019
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A local interconnect silicide structure (30) for connecting silicon regions (16) to silicon regions (20) separated by oxide regions (24) comprises a first portion of titanium silicide/titanium nitride/titanium silicide contacting the silicon regions and a second portion of titanium/titanium nitride/titanium silicide contacting the oxide regions. The silicide structure is also useful for connecting source/drain regions (14) and polysilicon interconnects (28). Two separate heating steps are employed, separated by an etch step to form the interconnects (34, 36). The first heating step forms (a) titanium silicides with single or polycrystalline silicon, using a first titanium layer (30a) at the bottom of the silicide structure and (b) titanium silicides with amorphous silicon (30d), using a second titanium layer (30c) on top of the titanium nitride layer (30b) on which the amorphous silicon is deposited and then patterned. The second heating step, which is at a higher temperature than the first, converts all the titanium silicides to titanium disilicide.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.