Trenched DMOS transistor with channel block at cell trench corners

US5468982A · kind A · utility

Assignee

• SILICONIX INCORPORATED · US

Inventors

• Fwu-Iuan Hshieh · Saratoga, US
• Sze-Hon Kwan · Sunnyvale, US
• Mike F. Chang · Cupertino, US
• Yueh-Se Ho · Sunnyvale, US
• Jan Van Der Linde · Saratoga, US
• King Owyang · Atherton, US

Key dates

• Filing date: Jun 3, 1994
• Grant date: Nov 21, 1995
• Expiry date: Jun 3, 2014

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/513

Abstract

A trenched DMOS transistor has improved device performance and production yield. During fabrication the cell trench corners, i.e. the areas where two trenches intersect, are covered on the principal surface of the integrated circuit substrate with a blocking photoresist layer during the source region implant step in order to prevent (block) a channel from forming in these corner areas. Punch-through is thereby eliminated and reliability improved, while source/drain on-resistance is only slightly increased. The blocking of the trench corners creates a cutout structure at each trench corner, whereby the source region does not extend to the trench corner, but instead the underlying oppositely-doped body region extends to the trench corner.