Method of making flash EEPROM memory with reduced column leakage current

US5482881A · kind A · utility

Assignee

• Advanced Micro Devices, Inc. · US

Inventors

• Jian Chen · San Jose, US
• Yuan Tang · San Jose, US
• Scott Luning · San Francisco, US
• Salvatore F. Cagnina · Los Altos, US

Key dates

• Filing date: Mar 14, 1995
• Grant date: Jan 9, 1996
• Expiry date: Mar 14, 2015

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B69/00

Abstract

A flash EEPROM having reduced column leakage current suitably includes cells with more uniform erase times arranged in an array. An intermediate n+ implant immediately following the DDI implant step suitably provides an enhanced doping profile in the tunneling region, which increases the rate at which F-N tunneling occurs to erase the cells, and which increases the uniformity of F-N tunneling rates among memory cells within the array. A thermal cycle drives the intermediate n+ implant deeper into the tunneling region. Alternatively, an n+ implant may be performed at a relatively large angle with respect to the semiconductor substrate, which improves the doping concentration in the tunneling region of the source.